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- 利用Verilog HDL语言进行数字系统设计实现秒表的设计，涵盖原理图设计、文本设计以及进行波形仿真，并有对应的报告。报告中还包括BCD/7段译码集成电路74LS47仿真实验、单管分压式稳定工作点偏置电路仿真实验和8路智力竞赛抢答器电路设计-Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design,
bcdflag
- verilog code bcd adder using flag register
BCDcoder
- 关于三位数的BCD转二进制，和二进制转BCD码。用verilog编写-BCD to Binary and Binary to BCD
bcd_adder
- BCD ADDER USING VERILOG
wb_i2c.tar
- Verilog code to change BCD format to Binary format-Verilog code to change BCD format to Binary format
b_to_bcd
- Verilog语言编写，二进制码转BCD码-Verilog language, binary code to BCD code
MTM_UEC1_lab04_raportfinalny
- verilog hdl BCD to 7seg converter with testing module
Bin2BCD
- FPGA代码，使用Verilog HDL语言实现4 bit二进制转换成BCD代码。原理是移位加三。-FPGA code, using Verilog HDL language is converted into a binary 4 bit BCD code. The principle is Shift-Add-3 .
SMG
- 实现将BCD码动态扫描显示在数码管上--verilog(The realization of dynamic scanning BCD code displayed on the digital tube --verilog)